1. FIELD OF THE INVENTION
The present invention relates to a process in which metal oxide semiconductor field effect transistors, (MOSFET), are fabricated, with specific process steps included to decrease the risk of junction punchthrough.
2. DESCRIPTION OF PRIOR ART
Very large scale integration, (VLSI), has allowed the semiconductor chip industry to increase circuit density while still maintaining, or reducing cost. This has been accomplished by ability of the semiconductor industry to fabricate silicon devices with sub-micron features, or micro-miniaturazation. The attainment of sub-micron features has been achieved mainly by advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching, (RIE). The use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images in photoresist to be routinely obtained. Similar advances in dry etching tools and processes have resulted in the successful transfer of these sub-micron images in photoresist, to underlying materials, used for the fabrication of advanced MOSFET devices.
However with the trend to smaller devices, specific yield detractors, and reliability risks, become more prevalent. For example as the gate insulator of a MOSFET device becomes thinner, in an attempt to improve device performance, the possibility of yield loss, due to insulator breakdown becomes greater. In addition as the channel length of the MOSFET becomes shorter, again to improve performance, the reliability risk of hot electron injection increase.
Narrower channel lengths also present yield problems in terms of junction punchthrough. As the channel length of a MOSFET device shortens, the space between depletion regions, created from the source region and the substrate, and from the drain region and substrate, decrease. This close proximity, or touching of depletion regions, can result in punchthrough leakages, or yield detractors. Several solutions for the punchthrough leakage phenomena have previously been described. For example Tsai, et al, in U.S. Pat. No. 5,108,937, describe a structure in which the polysilicon gate and gate insulator are recessed to a level equal to the bottom of the source and drain regions, to block the depletion regions from touching. This solution, although supplying protection from the punchthrough mechanism, results in additional complexity and costs. Other solutions offer increasing the doping level of the substrate, in the channel region and also in the source and drain regions. The increased doping levels of the substrate, reduce the severity of the depletion region. The increase of the substrate doping levels, specifically in the MOSFET channel region, is accomplished via an anti-punchthrough, ion implantation procedure. However the reduction in the yield degrading punchthrough leakages, is achieved at the expense of performance degrading increases in capacitances, due to the higher concentration of substrate doping in the source and drain channel region.
This invention will also describe an anti-punchthrough, ion implant solution, for narrow, sub-half micron, channel lengths. However this invention will describe a process that restricts the amount of substrate, experiencing the punchthrough implant, however still allowing reductions in depletion region formation, but not resulting in the level of capacitance increase observed with prior art, anti-punchthrough, ion implantation procedures.